#ifndef XPARAMETERS_H   /* prevent circular inclusions */
#define XPARAMETERS_H   /* by using protection macros */

#define XPAR_XGPIO_NUM_INSTANCES 1

/* Definitions for peripheral AXI_GPIO_0 */
#define XPAR_AXI_GPIO_0_COMPATIBLE xlnx,axi-gpio-2.0
#define XPAR_AXI_GPIO_0_BASEADDR 0x40000000
#define XPAR_AXI_GPIO_0_HIGHADDR 0x4000ffff
#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0x0
#define XPAR_AXI_GPIO_0_IS_DUAL 0x1
#define XPAR_AXI_GPIO_0_GPIO_WIDTH 0x10

/* Canonical definitions for peripheral AXI_GPIO_0 */
#define XPAR_XGPIO_0_BASEADDR 0x40000000
#define XPAR_XGPIO_0_HIGHADDR 0x4000ffff
#define XPAR_XGPIO_0_COMPATIBLE xlnx,axi-gpio-2.0
#define XPAR_XGPIO_0_GPIO_WIDTH 0x10
#define XPAR_XGPIO_0_INTERRUPT_PRESENT 0x0
#define XPAR_XGPIO_0_IS_DUAL 0x1

#define XPAR_XINTC_NUM_INSTANCES 1

/* Definitions for peripheral MICROBLAZE_0_AXI_INTC */
#define XPAR_MICROBLAZE_0_AXI_INTC_COMPATIBLE xlnx,axi-intc-4.1
#define XPAR_MICROBLAZE_0_AXI_INTC_BASEADDR 0x41200000
#define XPAR_MICROBLAZE_0_AXI_INTC_HIGHADDR 0x4120ffff
#define XPAR_MICROBLAZE_0_AXI_INTC_KIND_OF_INTR 0x2
#define XPAR_MICROBLAZE_0_AXI_INTC_IS_FAST 0x1
#define XPAR_MICROBLAZE_0_AXI_INTC_IVAR_RST_VAL 0x10
#define XPAR_MICROBLAZE_0_AXI_INTC_NUM_INTR_INPUTS 0x2
#define XPAR_MICROBLAZE_0_AXI_INTC_ADDR_WIDTH 0x20
#define XPAR_MICROBLAZE_0_AXI_INTC_OPTIONS 0x0
#define XPAR_MICROBLAZE_0_AXI_INTC_INTCTYPE 0x0
#define XPAR_MICROBLAZE_0_AXI_INTC_HANDLER_TABLE 0x0

/* Canonical definitions for peripheral MICROBLAZE_0_AXI_INTC */
#define XPAR_XINTC_0_BASEADDR 0x41200000
#define XPAR_XINTC_0_HIGHADDR 0x4120ffff
#define XPAR_XINTC_0_HANDLER_TABLE 0x0
#define XPAR_XINTC_0_ADDR_WIDTH 0x20
#define XPAR_XINTC_0_COMPATIBLE xlnx,axi-intc-4.1
#define XPAR_XINTC_0_IS_FAST 0x1
#define XPAR_XINTC_0_IVAR_RST_VAL 0x10
#define XPAR_XINTC_0_INTCTYPE 0x0
#define XPAR_XINTC_0_KIND_OF_INTR 0x2
#define XPAR_XINTC_0_NUM_INTR_INPUTS 0x2
#define XPAR_XINTC_0_OPTIONS 0x0

#define XPAR_XTMRCTR_NUM_INSTANCES 1

/* Definitions for peripheral AXI_TIMER_0 */
#define XPAR_AXI_TIMER_0_COMPATIBLE xlnx,axi-timer-2.0
#define XPAR_AXI_TIMER_0_BASEADDR 0x41c00000
#define XPAR_AXI_TIMER_0_HIGHADDR 0x41c0ffff
#define XPAR_AXI_TIMER_0_CLOCK_FREQUENCY 0x5f5e100
#define XPAR_AXI_TIMER_0_INTERRUPTS 0x2000
#define XPAR_AXI_TIMER_0_INTERRUPT_PARENT 0x41200001

/* Canonical definitions for peripheral AXI_TIMER_0 */
#define XPAR_XTMRCTR_0_BASEADDR 0x41c00000
#define XPAR_XTMRCTR_0_HIGHADDR 0x41c0ffff
#define XPAR_XTMRCTR_0_COMPATIBLE xlnx,axi-timer-2.0
#define XPAR_XTMRCTR_0_CLOCK_FREQUENCY 0x5f5e100
#define XPAR_XTMRCTR_0_INTERRUPTS 0x2000
#define XPAR_XTMRCTR_0_INTERRUPT_PARENT 0x41200001

#define XPAR_XUARTLITE_NUM_INSTANCES 1

/* Definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_AXI_UARTLITE_0_COMPATIBLE xlnx,axi-uartlite-2.0
#define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000
#define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060ffff
#define XPAR_AXI_UARTLITE_0_BAUDRATE 0x2580
#define XPAR_AXI_UARTLITE_0_USE_PARITY 0x0
#define XPAR_AXI_UARTLITE_0_ODD_PARITY 0x0
#define XPAR_AXI_UARTLITE_0_DATA_BITS 0x8
#define XPAR_AXI_UARTLITE_0_INTERRUPTS 0x1
#define XPAR_AXI_UARTLITE_0_INTERRUPT_PARENT 0x41200001

/* Canonical definitions for peripheral AXI_UARTLITE_0 */
#define XPAR_XUARTLITE_0_BASEADDR 0x40600000
#define XPAR_XUARTLITE_0_HIGHADDR 0x4060ffff
#define XPAR_XUARTLITE_0_BAUDRATE 0x2580
#define XPAR_XUARTLITE_0_COMPATIBLE xlnx,axi-uartlite-2.0
#define XPAR_XUARTLITE_0_DATA_BITS 0x8
#define XPAR_XUARTLITE_0_INTERRUPTS 0x1
#define XPAR_XUARTLITE_0_INTERRUPT_PARENT 0x41200001
#define XPAR_XUARTLITE_0_ODD_PARITY 0x0
#define XPAR_XUARTLITE_0_USE_PARITY 0x0

/* Definitions for peripheral PERTEST_0 */
#define XPAR_PERTEST_0_BASEADDR 0x44a00000
#define XPAR_PERTEST_0_HIGHADDR 0x44a0ffff

/*  BOARD definition */
#define XPS_BOARD_BASYS3

#define XPAR_LMB_BRAM_0_BASEADDRESS 0x0
#define XPAR_LMB_BRAM_0_HIGHADDRESS 0x20000
#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 100000000

#define XPAR_MICROBLAZE_ADDR_SIZE 32

#define STDOUT_BASEADDRESS 0x40600000
#define STDIN_BASEADDRESS 0x40600000

/* Number of SLRs */
#define NUMBER_OF_SLRS 0x1

/* Device ID */
#define XPAR_DEVICE_ID "7a35t"

#endif  /* end of protection macro */